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The GAPH Asynchronous Research Page

Since 2006, the GAPH dedicates a significant part of its efforts in research to investigate the design, test and implementation of asynchronous circuits.

The Group has addressed the research on several aspects of asynchronous design, including, but not restricted to:
  1. Asynchronous circuit design techniques
  2. Components for asynchronous circuits
  3. Standard cell libraries for asynchronous circuits
  4. Asynchronous design templates
  5. Asynchronous circuit implementation in both FPGAs and ASICs
  6. EDA methods and tools for asynchronous circuits

Most results of our research are described in the near 100 publications (as of today, June 2020) listed for example in Prof. Calazans homepage (external link).

In 2016 the GAPH hosted the 22nd edition of the ASYNC Symposium (external link), the first realized in the Southern hemisphere. The event (external link) took place here in Porto Alegre (external link), at the PUCRS (external link).

A significant amount of our efforts involves the development of asynchronous components (C-elements, NCL gates, etc.) and cell libraries of these for asynchronous design. A first library is the ASCEnD-ST65 library, the development of which started back in 2010. This library is developed using an ST Microelectronics 65nm bulk CMOS process design kit (PDK) and is compatible with the foundry sore library. Since such a library is bound be signed NDAs, it cannot be made available freely. This is not the case of another library we developed in-house, the ASCEnD-FreePDK45 library (external link), recently released as a Github project (external link).

One of our latest developments on research is the SDDS-NCL asynchronous design template. The link gives some details about this template, designed to enable the use of commercial design tools to seamlessly implement asynchronous circuits. The ASCEnD-FreePDK45 library (external link) supports this template.


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